1. Field of the Invention
The present invention relates to a semiconductor device having a general-purpose buffer including single-channel thin-film transistors formed on an insulator substrate. The buffer is not limited to any particular application but finds a variety of applications as devices and products. The present invention also related to a display panel and an electronic apparatus.
2. Description of the Related Art
Through a low-temperature polysilicon (LTPS) process, a circuit can be produced based on both an n-channel metal oxide semiconductor (NMOS) type thin-film transistor (TFT) and a p-channel metal oxide semiconductor (PMOS) type TFT. A complementary metal oxide semiconductor (CMOS) circuit is thus typically manufactured based on the two types of thin-film transistors.
Since the CMOS circuit is composed of the two types of thin-film transistors, the number of process steps is increased. An increase in the number of process steps becomes one of the causes lowering production yield, and increasing manufacturing costs.
Even when a polysilicon process is used, a circuit having the same function as the CMOS is preferably constructed of single-channel thin-film transistors (either NMOS or PMOS thin-film transistors).
Such a single-channel circuit can find applications where amorphous silicon or organic semiconductor is used.
For example, amorphous silicon permits a circuit to be manufactured of an NMOS thin-film transistor only, and organic thin-film transistor permits a circuit be manufactured of a PMOS thin-film transistor only.
There is a need for a circuit made of a single-channel thin-film transistor only (either NMOS thin-film transistor or PMOS thin-film transistor) and able to execute the same function as a CMOS circuit.
A buffer is described in particular in this specification. The buffer is a widely used circuit finding a variety of applications. The buffer is thus not limited to any particular application. For convenience of explanation, however, the buffer is described below on the premise that the buffer is applied to a driver driving a display panel.
A buffer in the related art described below is applied as a driver for an active-matrix driving, organic electroluminescence (EL) panel as disclosed in Japanese Unexamined Patent Application Publication No. 2005-149624.
FIG. 1 illustrates a system configuration of an organic EL panel 1. The organic EL panel 1 illustrated in FIG. 1 includes a pixel array 3 on a panel substrate, a signal line driver 5, a first control line driver 7, and a second control line driver 9.
Sub pixels 11 are arranged in a matrix on the pixel array 3 in accordance with a display resolution. FIGS. 2 and 3 illustrate an equivalent circuit of the sub pixel 11. Each sub pixel 11 is constructed of NMOS thin-film transistors only.
As shown in FIGS. 2 and 3, N1 denotes a sampling transistor, N2 denotes a driver transistor, N3 denotes a light-on control transistor, and Cs denotes a hold capacitor. WSL denotes a write control line, LSL denotes a light-on control line, and PSL denotes a current supply line.
FIG. 2 illustrates a circuit operating in a drive method in which a light-on operation and a light-off operation of an organic EL element OLED are controlled in response to on-off control of the light-on control transistor N3.
FIG. 3 illustrates a circuit operating in a drive method in which the light-on operation and the light-off operation of the organic EL element OLED are controlled in response to a voltage change of the light-on control line LSL. Referring to FIG. 3, the light-on control line LSL also serves as a current supply line.
FIG. 4 is a timing diagram of a write operation in which a signal voltage Vsig (Data) is written onto the sub pixel 11 illustrated in FIGS. 2 and 3. FIG. 4 illustrates a drive waveform of a signal line DTL. The signal line DTL is supplied with the signal voltage Vsig responsive to pixel gradation Data. The magnitude of the signal voltage Vsig determines the magnitude of a drive current supplied by the driver transistor N2. The organic EL element OLED is a current driving element. The higher the drive current, the higher luminance results.
FIG. 4 also illustrates the write control line WSL. The sampling transistor N1 is conductive during a high-level period of the write control line WSL, and a voltage of the signal line DTL is written on a gate electrode of the driver transistor N2.
FIG. 4 also illustrates the light-on control line LSL. The light-on control line LSL is driven between a high level and a low level. With the voltage transition of the light-on control line LSL, the organic EL element OLED is switched between a light-on state and a light-off state.
The control amplitude of the light-on control line LSL is different from the sub pixel 11 illustrated in FIG. 2 to the sub pixel 11 illustrated in FIG. 3. As illustrated in FIG. 2, the light-on control line LSL simply drives the light-on control transistor N3. As illustrated in FIG. 3, the light-on control line LSL supplies an operating voltage to both the driver transistor N2 and the organic EL element OLED.
Referring to FIG. 4, after the write operation of the signal voltage Vsig, the organic EL element OLED is lit with the light-on control line LSL at a high level and the organic EL element OLED is extinguished with the light-on control line LSL at a low level.
A peak luminance level can be controlled by varying the duty factor of a light-on period to one field.
The light-on control line LSL (FIG. 4) is also used to adjust moving image characteristics. In order to adjust the moving image characteristics, the number of lightings and the timing of the light-on period within one field are adjusted.
A plurality of types of pulses are thus output from the second control line driver 9.
The pulses are then transferred in line-at-a-time scanning order in order to perform a typical ling-at-a-time scanning write operation on the active-matrix driving method.
More specifically, the control line driver has a function of permitting a pulse length of a control pulse to be freely set and a function of permitting the control pulse to be transferred to a next stage.
During the write operation of the signal voltage Vsig on the sub pixels 11 illustrated in FIGS. 2 and 3, a threshold offset operation and a mobility correction operation of the driver transistor N2 are also performed. FIG. 5 is a timing diagram of the sub pixel 11 illustrated in FIG. 2. It is noted that if the sub pixel 11 illustrated in FIG. 2 has the correction functions, the current supply line PSL is driven as illustrated in FIG. 5. FIG. 6 is a timing diagram of the sub pixel 11 illustrated in FIG. 3. The difference between the sub pixel 11 illustrated in FIG. 2 and the sub pixel 11 illustrated in FIG. 3 is related to whether an initialization operation is separated from light emission period control.
In the light emission period control, a duty factor of a light-on period to a light-off period is varied in order to adjust the peak luminance. Also in the light emission period control, the number of switchings between the light emission period and the light-off period within one field is modified. For these operations, the circuit structure of the second control line driver 9 become typically complex.
In the circuit structure illustrated in FIG. 2, the current supply line PSL for an initialization pulse for a preliminary timing of a threshold offset period is separated from the light-on control line LSL for the light-off period control pulse. The circuit structure illustrated in FIG. 2 is advantageous in view of simplification of a control interface. The circuit structure illustrated in FIG. 2 employs three control lines of the write control line WSL, the light-on control line LSL, and the current supply line PSL.
The threshold offset operation, the mobility correction operation, and a control operation of the sub pixel 11 including the light emission period control are described with reference to the pixel circuit illustrated in FIG. 3 in view of FIG. 6.
The control operation for the pixel circuit illustrated in FIG. 2 is generally similar to the control operation for the pixel circuit illustrated in FIG. 3 except that the initialization operation is separated from the light emission period control, and the discussion of the control operation for the pixel circuit illustrated in FIG. 2 is omitted here.
FIG. 6 illustrates the drive waveform of the signal at the write control line WSL. During a high level period of the write control line WSL, the sampling transistor N1 is conductive, and the voltage the signal line DTL is written on the gate electrode of the driver transistor N2.
The first high level period of the write control line WSL is used to correct variations of a threshold voltage value Vth of the driver transistor N2.
The second high level period of the write control line WSL is used to write the signal voltage Vsig responsive to the pixel gradation and to correct variations in mobility μ of the driver transistor N2.
The falling edge of the second high level period is sloped to set a mobility correction period optimum for all gradations ranging from the highest luminance level (high voltage signal) down to the lowest luminance level (low voltage signal).
The mobility correction operation is to correct a difference between the driver transistor N2 having a high mobility μ and the driver transistor N2 having a low mobility μ. A correction period is determined by the length of the high level period of the write control line WSL. The correction period becomes longer as the low luminance (low voltage signal) period is longer.
FIG. 6 also illustrates the drive waveform of the signal at the signal line DTL. The signal line DTL is supplied with voltages of the two levels. An offset voltage Vofs is used to offset the threshold value of the driver transistor N2. The signal voltage Vsig results in a pixel gradation. The magnitude of the signal voltage Vsig determines the drive current supplied by the driver transistor N2. The organic EL element OLED is a current driven element, and provides a higher luminance in response to a higher drive current.
FIG. 6 also illustrates the drive waveform of the signal at the light-on control line LSL. The light-on control line LSL is driven at either of the two levels of a high level and a low level. The first low level period of the light-on control line LSL serves as an initialization period. The second low level period serves as a light-off period subsequent to the start of light emission.
The initialization operation herein causes a gate-source voltage Vgs of the driver transistor N2 to be wider in voltage range than the threshold voltage value Vth. The initialization operation is performed prior to the execution of the threshold offset operation. The initialization operation is hereinafter referred to as a offset preparation operation.
Subsequent to the offset preparation operation, the gate electrode of the driver transistor N2 is supplied with the offset voltage Vofs and the voltage at the light-on control line LSL is transitioned to the high level. This operation related to voltage level is the threshold offset operation. When the threshold offset operation starts, a source voltage Vs of the driver transistor N2 gradually rises. At the moment the gate-source voltage Vgs of the driver transistor N2 reaches the threshold voltage value Vth, the source voltage Vs stops rising.
When the write operation of the signal voltage Vsig is completed, the light emission period starts and continues until a next write operation period. During the light emission period, the organic EL element OLED is lit with the light-on control line LSL at a high level and is extinguished with the light-on control line LSL at a low level. The peak luminance level is controlled by varying the duty factor of the length of the light-on period within one field.
FIG. 6 illustrates the signal voltage Vg appearing at the gate electrode of the driver transistor N2. Also, FIG. 6 illustrates the voltage Vs appearing at the source electrode of the driver transistor N2 (positive electrode of the organic EL element OLED).
As previously discussed, the write control signal at the write control line WSL and the light-on control signal at the light-on control line LSL illustrated in FIG. 6 become different in length depending on the purpose of driving operation.
For example, the write control signal at the write control line WSL becomes different in pulse length from the threshold offset operation to a signal write and mobility correction operation. The light-one control signal at the light-on control line LSL becomes different in pulse length from the threshold offset operation to the light-on/light-off control in the light emission period.
Each of the first control line driver 7 and the second control line driver 9 thus outputs pulses of a plurality of different pulse lengths. In the case of the line-at-a-time scanning typical of the active-matrix driving method, these pulse waveforms are transferred on a line-at-a-time scanning basis. This type of control line driver has to have the two functions, i.e., a function of setting freely the pulse length of the control pulse and a function of transferring the control pulse to the subsequent stage on a line-at-a-time scanning basis.
FIGS. 7-14 illustrate examples and driving operations of the control line driver satisfying the above-described condition. The control line driver here is composed of a shift register.
The shift register illustrated in FIG. 7 includes 2N cascaded shift stages SR(1)-SR(2N). Each shift stage uses output pulses from other shift stages present prior to and subsequent to the shift stage, and outputs a clock signal input thereto as an output pulse.
FIG. 8 illustrates drive pulse waveforms of the shift register. The pulse waveforms illustrated in FIG. 8 are caused by the shift register that is manufactured of NMOS thin-film transistors only.
FIG. 8 also illustrates the start pulse st for driving the first shift stage, an end pulse end for driving the 2N-th shift stage, and a clock signal ck1 for shift stages positioned at even-numbered stages.
FIG. 8 also illustrates a clock signal ck2 for shift stages positioned at odd-numbered stages, and an output pulse o1 of the shift stage SR(1). FIG. 8 also illustrates an output pulse o(k−1) of the shift stage SR(k−1) at the (k−1)-th stage. FIG. 8 also illustrates output pulses o at respective shift stages.
FIG. 9 illustrates an internal circuit example of the shift stage SR at the k-th stage. As illustrated in FIG. 9, thin-film transistors forming the shift stage SR are all NMOS types. The output of the shift stage NMOS SR includes thin-film transistors N11 and N12 connected in series between a power source voltage VSS and a clock input terminal. An intermediate junction point between the thin-film transistors N11 and N12 is connected to an output terminal. A auxiliary capacitance Cb1 is connected between the gate electrode of the thin-film transistor N11 and the power source voltage VSS. On the other hand, the auxiliary capacitance Cb2 is connected between the gate electrode of the thin-film transistor N12 and the clock input terminal. The auxiliary capacitance Cb2 assists in a bootstrap operation.
FIG. 10 illustrates the relationship of input and output pulses and voltages at nodes A and B of the shift stage SR. FIG. 10 also illustrates the waveforms of a clock signal ck, a first drive pulse in(k)(output pulse out(k−1) of the immediately preceding shift stage), and a second drive pulse in2(k) (output pulse out(k+1) of the immediately subsequent shift stage). FIG. 10 also illustrates the waveforms of a voltage at node B (control line voltage of the thin-film transistor N11), a voltage at node A (control line voltage of the thin-film transistor N12), and an output pulse out appearing at the output terminal.
Referring to FIG. 10, the voltages at nodes A and B are complementarily switched at each of the timing of the rising edge of the high level of the first drive pulse in1(k) and the timing of the rising edge of the high level of the second drive pulse in2(k).
This complementary operation is performed by thin-film transistors N13-N16.
With the first drive pulse in1(k) at the high level and the first drive pulse in2(k) at the low level, the thin-film transistors N13 and N14 are conductive and the thin-film transistors N15 and N16 are non-conductive. With the first drive pulse in1(k) at the low level and the first drive pulse in2(k) at the high level, the thin-film transistors N13 and N14 are non-conductive and the thin-film transistors N15 and N16 are conductive.
The auxiliary capacitance Cb2 is charged with the node A at the high level. The output pulse out(k) is transitioned to the high level with the node A at the high level at the timing the clock signal ck is transitioned to the high level. The voltage at the node A is raised by a charge voltage of the auxiliary capacitance Cb2. The gate-source voltage Vgs of the thin-film transistor N12 is maintained at a voltage equal to or higher than the threshold voltage value Vth in accordance with the bootstrap operation. The voltage waveform of the output pulse out(k) is identical to the voltage waveform of the clock signal ck.
The shift register illustrated in FIG. 7 picks up the clock signal ck from the shift stages, starting with the first shift stage and then outputs the clock signal ck. The variable range of the pulse width of the output pulse out is thus limited to a range of 1 H (horizontal scanning period) within which the pulse width of the clock signal ck is variable.
The shift register can transfer a plurality of pulse signals within the 1 H period.
FIG. 11 illustrates a transfer operation with the clock signal ck containing two pulses. The waveforms illustrated in FIG. 11 respectively correspond to the waveform diagrams illustrated in FIG. 8.
FIG. 12 illustrates the drive waveforms of the signals at the shift stage SR, respectively corresponding to the waveforms illustrated in FIG. 10. Referring to FIG. 12, the bootstrap operation is also performed with the two pulses.
The shift register illustrated in FIG. 7 can reproduce the same waveform in the output pulse by adjusting the rising rate and the falling rate of the clock signal ck.
FIG. 13 illustrates a transfer operation when a trapezoidal clock signal ck is input as the clock signal ck. The drive waveforms illustrated in FIG. 13 correspond to the drive waveforms illustrated in FIG. 8.
FIG. 14 illustrates the drive waveforms of the shift register. The drive waveforms illustrated in FIG. 14 respectively correspond to the drive waveforms illustrated in FIG. 10. The bootstrap operation is performed in accordance with the same trapezoidal waveform as the clock signal ck and the output pulse out has the same trapezoidal waveform.